1. Field of the Invention
The present invention relates to a non-volatile memory device using a MOS transistor having a floating gate, and relates to a memory device consuming little current and allowing high speed reading.
2. Description of the Related Art
Non-volatile memory, using MOS transistors having floating gates as memory cells, is widely used because the high volume of data stored is not volatile. In particular, flash memory, which has a simplified circuit structure wherein the units erased are limited to relatively large blocks, is in widespread use. This flash memory is a device having normal memory blocks for storing data, as well as a boot block with a smaller capacity. This boot block is an area that is unconditionally accessed at the startup of a system which includes flash memory, for example. Such a boot block houses a top boot block disposed on the upper address side of the block and a bottom boot block disposed on the lower address side. The only difference between these is whether the upper address or lower address is the block selection address which is initially accessed. The memory devices within the boot block are the same.
Flash memory having such a boot block must be the top boot block type or the bottom boot block type, depending on the users' requirements. Consequently, a single type of memory device is manufactured; the information about the type selected according to the users' requirements is stored in the function setting memory; and the block selection address Add1 is switched according to the function setting bit.
FIG. 6 is a figure showing an example of the constitution of the conventional function setting memory. In the constitution of the conventional memory, like in a normal memory cell, a MOS transistor T3 having a floating gate and which stores data and the load transistor T2 thereof are serially connected between the power source Vcc and ground GND. The load transistor T2 is an P-channel enhance transistor, for example; its gate is maintained at ground potential and it has a prescribed impedance and is continually in a conductive state. The MOS transistor T3 has a floating gate FG. The threshold voltage of the transistor T3 is increased by writing (programming), by adding electrons to the floating gate FG; the threshold voltage thereof is decreased by erasing, by pulling out electrons from the floating gate FG. Consequently, the application of a voltage at a level between these threshold voltages to the control gate CG causes the MOS transistor T3 to become conductive or non-conductive in accord with the stored data.
A prescribed control voltage must be applied to the source and drain of the MOS transistor T3 in order to add or pull electrons from the floating gate FG of the MOS transistor T3. However, it is difficult to apply such a control voltage because the MOS transistor T3 has the circuit structure shown along with the load transistor T2. A separate transistor T4, for writing and erasing and which shares the floating gate FG, is therefore established. The operations of adding and pulling electrons from the floating gate FG is carried out by means of this transistor T4.
This type of memory is read by applying a voltage between the aforementioned threshold voltages to the control gate CG, making the transistor T3 conductive or non-conductive, and detecting the voltage of the contact n12 of the transistors T2, T3. The voltage of the contact point n12 is read from the output OUT by means of inverters 10, 11. In the case where writing is being performed, the transistor T3 becomes non-conductive, the contact point n12 becomes H level, and the output OUT also becomes H level. In the erasing state, the transistor T3 is conductive, the contact point n12 becomes L level, and the output OUT also becomes L level.
In the memory device constitution shown in FIG. 6, when the read voltage is applied to the control gate CG with the transistor T3 in the erasing state, the transistor T3 becomes conductive and the through current flows from the power source Vcc to the transistors T2, T3, and the ground. This current brings about an increase in power consumption. In the power down state where reading is not performed, it is necessary that the control gate CG be kept at ground potential so that through current does not flow, regardless of whether the transistor T3 is in the erasing state or writing state. The potential of the CG rises from ground to a prescribed reading potential only upon transition to an active state for reading data.
Consequently, when using the function setting memory in the memory device constitution shown in FIG. 6, the access time for entering the active state becomes long, because it is necessary to raise the control gate CG of the function setting memory and read the setting information before accessing normal memory.
A redundant memory cell array is included to compensate for bad bits of high capacity flash memory. The redundant ROM stores the address of those bad bits and makes it necessary to raise the control gate CG of the memory device to read the redundant ROM each time the memory is accessed, when using the memory device as shown in FIG. 6 as the redundant ROM. Consequently, this redundant ROM is in concept a type of function setting memory and becomes an obstacle to increasing the speed of a memory device as in FIG. 6.